GIB: A Novel Unidirectional Interconnection Architecture for FPGA

摘要

Field Programmable Gate Arrays (FPGAs) are widely used because of the superiority in flexibility and low nonrecurring engineering cost. The routing architecture has a large impact on the FPGA area, delay and routability. Hence, it is important to optimize the routing architecture. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs), while most researches have focused on the SB architectures, such as Wilton, Universal and Disjoint SB patterns. In this paper, we propose a novel unidirectional routing architecture, general interconnection block (GIB) to improve the routability and performance. With GIB architecture, logic block (LB) pins can directly connect with the adjacent GIBs without programmable switches. Inside a GIB, LB pins and wire segments can connect with each other flexibly. LB pins can connect to the routing channel tracks on the four sides of a GIB. In particular, the logic pins from different neighboring LBs that connect to the same GIB can connect with each other with only one programmable switch which is impossible in the CB-SB architecture. We evaluate the GIB architecture on VTR 8 with the provided benchmark circuits. The experimental results show that the GIB architecture with all length-4 wires, which can offer the best area-delay tradeoff among the single wire types, achieves 8.3% improvement on the critical path delay and 9.9% improvement on the area-delay product on average compared to the VTR CB-SB architecture with the equivalent CB flexibility ($fc$) and SB flexibility ($fs$) values. In addition, it can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product after exploring different $fc$ and $fs$ values with all length-4 wires.