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Accurately measure phase-locked loop lock time in production

机译:准确测量生产中锁相环锁定时间

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This paper introduces the method to accurately measure Phase-locked loop (PLL) lock time in a multi-site production environment. This method is also applicable for measuring RF transceiver frequency settling time, frequency and phase errors after settling for multiple devices under test (DUT) in parallel using either on board frequency mixers and RF signal generators or using RF receivers of automated test equipment (ATE).
机译:本文介绍了在多站点生产环境中精确测量锁相环(PLL)锁定时间的方法。这种方法还适用于测量RF收发器频率沉降时间,频率和相位误差在耦合频率混频器和RF信号发生器上并行沉降测试(DUT),或者使用自动测试设备的RF接收器(ATE) 。

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