A 10.6#x03BC;m #x00D7; 10.6#x03BC;m CMOS SPAD with integrated readout

摘要

Single photon avalanche diodes (SPAD) are sensitive optical sensing tools. Incoming photons trigger avalanche events resulting in large device currents. In this paper, we show experimental results for a 10.6 μm × 10.6 μm perimeter gated SPAD with integrated readout circuitry in 0.5 μm 2 poly, 3 metal standard CMOS process. The dark count rate demonstrates a functional relationship with the gate and the excess bias voltage. A compact readout topology is used which takes advantage of the Miller effect to reduce the readout area footprint, thus increasing the pixel fill factor.