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Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations

机译:用大规模过程和环境变化定义逻辑电路定时优化统计敏感性

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The large-scale process and environmental variations for today's nanoscale ICs are requiring statistical approaches for tuning analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how one should interpret the statistical timing results for optimization. In this paper [1] we demonstrate why the traditional concepts of slack and critical path become ineffective under large-scale variations, and we propose a novel sensitivity-based metric to assess the "criticality" of each path and/or arc in the statistical timing graph. We define the statistical sensitivities for both paths and arcs, and theoretically prove that our path sensitivity is equivalent to the probability that a path is critical, and our arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.
机译:今天纳米级IC的大规模过程和环境变化需要统计调整分析和优化的统计方法。最近侧重于开发新的统计时序分析算法的重要研究,但通常不考虑如何解释优化的统计时间结果。在本文[1]中,我们展示了在大规模变化下的传统概念和关键路径的传统概念无效,我们提出了一种新颖的敏感性的公制,以评估每个路径和/或校准中的acc的“临界”时序图。我们为路径和弧定义统计敏感性,理论上证明我们的路径敏感性等同于路径至关重要的概率,并且我们的电弧灵敏度相当于弧坐在关键路径上的概率。具有增量分析能力的高效算法,用于快速灵敏度计算,其在电路大小中具有线性运行时复杂度。所提出的敏感性分析的功效在标准基准电路和大型行业示例中证明。

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