A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors

摘要

This paper describes a configurable platform chip integrating 9 heterogeneous processors, which is designed to enable rapid prototyping and verification without translating functional behaviors into hardware blocks. The chip consists of a 32-bit multithreaded RISC processor for fast context switching, four 32-bit SIMD processors for data-intensive applications, and four IO processors for handling I/O protocols. The prototype chip has been designed and fabricated in 0.25-/spl mu/m CMOS technology and the die size is 8/spl times/8 mm/sup 2/ including eighty-kilobyte internal memories.