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Scaling Challenges of NAND Flash Memory and Hybrid Memory System with Storage Class Memory NAND flash memory

机译:使用存储类内存和NAND闪存的NAND闪存和混合存储系统的缩放挑战

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This paper summarizes the scaling challenges of the conventional 2D floating-gate cell NAND flash memories [1, 2]. The scaling trends and limits of the bulk and SOI NAND flash memories are investigated in terms of short channel effects and channel boosting leakage from 20nm to below 10nm generation using 3D-device simulation. In the bulk NAND cell, 13nm generation is the scaling limit for realizing both channel boosting during program-inhibit and SCE suppression. The SOI NAND cell scaling limit is decreased to 8nm generation. Then, scaling problems and device design for 3D-stackable NAND flash memory are investigated [3]. Control gate length (L_g) and spacing (L_(space)) are P~aid attention since they can be separately varied in 3D NAND and significantly affect the cell area of the 3D NAND as well as the electrical characteristics. L_g and L_(space) should be the same to cope with the tradeoff between memory window and disturbance. If the number of stacked layers is 18 with the layer pitch of 40nm, the effective cell size of the 3D NAND corresponds to that of 15nm planar NAND technology. Then, this paper discusses an error prediction (EP) low density parity check (LDPC) error correcting code (ECC) which realizes an over 10-times extended lifetime [4, 5]. As the design rule shrinks, the floating gate (FG)-FG capacitive coupling among neighboring memory cells seriously degrades the memory cell reliability. The EP-LDPC ECC calibrates the inter-cell coupling without access time penalty. Finally, this paper overviews a state-of-the-art hybrid memory solution with storage class memory (SCM) and NAND flash memory for the big data solid-state storage system [5, 6]. Data fragmentation of MLC NAND flash memory is suppressed and efficient MLC NAND flash usage is realized by storing small hot data to SCM. The 3D TSV hybrid SSD realizes 11 times performance increase, 6.9 times endurance enhancement and 93% write energy reduction.
机译:本文总结了传统的2D浮栅电池NAND闪存[1,2]的缩放挑战。在使用3D设备模拟的情况下,根据短信效应和频道提高20nm至10nm的通道泄漏的尺寸和SOI NAND闪存的缩放趋势和限制。在散装NAND单元中,13nm代是在程序禁止和SCE抑制期间实现频道升高的缩放限制。 SOI NAND细胞缩放限制减少到8nm。然后,研究了3D堆叠NAND闪存的缩放问题和设备设计[3]。控制栅极长度(L_G)和间隔(L_(空间))是P〜AID注意,因为它们可以在3D NAND中单独变化,并且显着影响3D NAND的单元面积以及电特性。 L_G和L_(空间)应相同,以应对内存窗口和干扰之间的权衡。如果堆叠层的数量为18,则具有40nm的层间距,3D NAND的有效小区尺寸对应于15nm平面NAND技术。然后,本文讨论了误差预测(EP)低密度奇偶校验(LDPC)纠错码(ECC),其实现了超过10倍的扩展寿命[4,5]。随着设计规则收缩,相邻存储器单元之间的浮栅(FG)-FG电容耦合严重降低了存储器单元可靠性。 EP-LDPC ECC校准群间耦合而无需访问时间损失。最后,本文概述了具有存储类存储器(SCM)和NAND闪存的最先进的混合存储器解决方案,用于大数据固态存储系统[5,6]。 MLC NAND闪存的数据碎片被抑制,并且通过将小型热数据存储到SCM来实现有效的MLC NAND闪存使用。 3D TSV杂交SSD实现了11次性能增加,6.9倍耐力增强和93%的写入能量减少。

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