This paper summarizes the scaling challenges of the conventional 2D floating-gate cell NAND flash memories [1, 2]. The scaling trends and limits of the bulk and SOI NAND flash memories are investigated in terms of short channel effects and channel boosting leakage from 20nm to below 10nm generation using 3D-device simulation. In the bulk NAND cell, 13nm generation is the scaling limit for realizing both channel boosting during program-inhibit and SCE suppression. The SOI NAND cell scaling limit is decreased to 8nm generation. Then, scaling problems and device design for 3D-stackable NAND flash memory are investigated [3]. Control gate length (Lg) and spacing (Lspace) are paid attention since they can be separately varied in 3D NAND and significantly affect the cell area of the 3D NAND as well as the electrical characteristics. Lg and Lspace should be the same to cope with the tradeoff between memory window and disturbance. If the number of stacked layers is 18 with the layer pitch of 40nm, the effective cell size of the 3D NAND corresponds to that of 15nm planar NAND technology. Then, this paper discusses an error prediction (EP) low density parity check (LDPC) error correcting code (ECC) which realizes an over 10-times extended lifetime [4, 5]. As the design rule shrinks, the floating gate (FG)-FG capacitive coupling among neighboring memory cells seriously degrades the memory cell reliability. The EP-LDPC ECC calibrates the inter-cell coupling without access time penalty. Finally, this paper overviews a state-of-the-art hybrid memory solution with storage class memory (SCM) and NAND flash memory for the big data solid-state storage system [5, 6]. Data fragmentation of MLC NAND flash memory is suppressed and efficient MLC NAND flash usage is realized by storing small hot data to SCM. The 3D TSV hybrid SSD realizes 11 times performance increase, 6.9 times endurance enhancement and 93% write energy reduction.
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机译：本文总结了常规2D浮栅单元NAND闪存的缩放挑战[1、2]。使用3D器件仿真，从短通道效应和从20nm到10nm以下的通道提升泄漏方面研究了大容量和SOI NAND闪存的缩放趋势和极限。在块状NAND单元中，13nm的产生是在编程禁止和SCE抑制期间实现通道提升的缩放极限。 SOI NAND单元的缩放比例限制减小到8nm。然后，研究了3D可堆叠NAND闪存的扩展问题和器件设计[3]。由于控制栅长度（Lg）和间距（Lspace）在3D NAND中可以分别变化，并且会显着影响3D NAND的单元面积以及电气特性，因此应引起注意。 Lg和Lspace应该相同，以应对内存窗口和干扰之间的折衷。如果堆叠的层数为18，层间距为40nm，则3D NAND的有效单元尺寸对应于15nm平面NAND技术的有效单元尺寸。然后，本文讨论了可实现超过10倍的扩展寿命的错误预测（EP）低密度奇偶校验（LDPC）纠错码（ECC）[4，5]。随着设计规则的缩小，相邻存储单元之间的浮栅（FG）-FG电容耦合严重降低了存储单元的可靠性。 EP-LDPC ECC校准小区间耦合，而不会影响访问时间。最后，本文概述了针对大数据固态存储系统的具有存储类存储器（SCM）和NAND闪存的最新混合存储解决方案[5，6]。通过将少量热数据存储到SCM，可以抑制MLC NAND闪存的数据碎片，并实现有效的MLC NAND闪存使用。 3D TSV混合固态硬盘可实现11倍的性能提升，6.9倍的耐用性增强和93％的写入能耗降低。
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