Reverse Engineering Register to Variable Mapping in High-level Synthesis

摘要

This paper presents a framework for reverse engineering of the register to variable mapping in high-level synthesis (HLS). The proposed framework helps to get back an equivalent C code from the RTL code generated by the HLS tools. The framework first extracts a high-level behaviour (RTL-C) from the RTL. The scheduled C code (SD-C) is then obtained by decoding the scheduling information. The SD-C code and RTL-C are then combined state wise manner. Finally, the state wise mapping between registers in RTL-C and variables in SD-C is extracted using an invariant generator tool Daikon on the combined program. The RTL-C is then rewritten with this mapping information to obtain an equivalent C code from the RTL. Our framework can be utilized by the algorithm developers to use HLS tools efficiently. It also can be used for faster simulation-based verification of HLS. The framework is implemented and tested on a commercial HLS tool for several benchmark designs.