Process variation-tolerant 3D microprocessor design: An efficient architectural solution

摘要

Process variation is one of the most challenging problems for 3D microprocessors. This is because stacked dies are likely to have fairly different characteristics due to wafer-to-wafer (W2W) variations, which may severely hurt yield of 3D microprocessors. In this paper, we introduce a process variation-tolerant 3D microprocessor design that exploits an architectural insight: narrow-width values. The main target of our technique is last-level caches (LLCs), which are composed of several dies. By storing only the meaningful bit parts within a data word into the LLCs while discarding the zero bit parts (which can be recovered by the zero-extension logic), our proposed technique improves a storage efficiency of the LLCs, which eventually enhances cache yield. According to our evaluation results, our technique significantly improves cache yield in a performance-/energy-efficient manner.