An efficient metric of setup time for pulsed flip-flops based on output transition time

摘要

In this paper, a new metric to compute the setup time of pulse-triggered flip-flops (pulsed-FFs) is proposed. With the emergence of new technologies, digital circuits are pushing towards high-speed and energy efficient modes. Setup time is an essential aspect of the timing constraints of a synchronous digital circuit. It is a key parameter to determine the minimum clock cycle, which gives the timing and energy performances of circuits. Due to their small input-to-output delay (D-to-Q), pulsed-FFs are key candidate to be the determinant sequential cell of high-speed but also energy efficient circuits. This paper shows that, for pulsed-FFs, the conventional setup time metric based on minimum data-to-output delay is loosely extracted during automatic standard-cell characterization. Thereby, we propose a new metric for characterizing the setup time of pulsed-FFs based on the output transition time. Quantitative and qualitative advantages of the proposed metric are validated with SPICE simulations in 28nm fully-depleted silicon on insulator (FDSOI) technology. The obtained gain motivates a potential integration into standard-cell characterization tools.