A 10Bit, 10MS/s, low power cyclic ADC

摘要

A low power, small form factor, cyclic ADC is proposed. By replacing the MDAC with an open loop residual amplifier, it relaxes the gain bandwidth requirement of the operational amplifier to save power. The residual amplifier is background calibrated without extra replica to avoid performance mismatches, and also save area and power. Timing reschedule scheme is proposed for each conversion step to accelerate conversion speed. At 10 MS/s operation, the corresponding FOM is 0.45pJ/conv.-step. Fabricated in a 85nm CMOS technology, the chip size is 0.077mm2.