A New Frequency Synthesizers Stabilization Method Based On a Mixed Phase Locked Loop and Delay Locked Loop Architecture

摘要

A novel technique for the stabilization of local oscillators is presented in this paper based on the combination of a Phase Locked Loop (PLL) and Delay Locked Loop (DLL) architecture. On one hand, phase noise performances are improved taking advantage of the both architecture and more particular to the non-accumulation of random timing jitter. On the other hand, such a methodology could relax constraints on the loop filter and it would then be possible to increase the architecture bandwidth without taking care of stability drawbacks. By the way, the settling time could be largely improved.