A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision

摘要

We present a design of a 2 to 12 port scalable multiport compiler with simultaneous read port access and closely packed graphics integration capability specially designed for low power high bandwidth, low latency stream vector processors and machine learning applications. Novel pipe-lined decoder and bitline repeater insertion helps to achieve a fast cycle time. Memory words can be accessed in different ways, serial, parallel or mixed. A wide supply range from 0.4V to 1.1V is supported without any complex write or read assist circuit. Design is non-self-timed and fully testable while timing and power views are generated through a static timing analysis (STA) approach. Layout is based on automatic place and route of standard cells in periphery and full custom standard cell compatible high density memory core. Full custom core is tightly bound with the common graphics processing operations, to enable low latency (<; 1μs), high bandwidth operations at low voltage. Hybrid approach reduces the turn around time to just a few man weeks. Area penalty of a 2W2R 64 Kbit instance is up to 10% in comparison to a logic rule based full custom high speed 1W1R compiler, while doubling the throughput. Compared to complete RTL based synthesis approach, area is just 5% for 64 Kbit. A 2W2R 32×128 testchip instance in sub-20nm FinFET process, runs up-to 3 GHz on CAD at 1.1 V supply at -40 °C. While measured speed of same instance on silicon is 86 MHz (at 0.42 V) for simultaneous access from both the ports and energy consumed is just 5 pJ/cycle in typical process corner. Architecture is scalable up to 64KB for more parallel architectures (64 cores) as demanded in ultra-high definition real time computational photography [1].