Hardware reduction using a 6-connectivity interconnection network over a 4-connectivity VLSI asynchronous array processor

摘要

Low level local image processing is efficiently performed by array processors operating in SIMD mode. Performing mid-level regional image processing leads to use local combinatorial operators combined with an asynchronous programmable interconnection network. However, this approach has an important hardware cost because asynchronism implies the use of combinatorial operators with many inputs. This cost should be reduced for a dense VLSI implementation. To do so, we propose to increase the connectivity level of the interconnection network as a mean to use only 2-input asynchronous combinatorial operators. Results are presented on the example of the regional sum mid-level primitive in vision chips. An extension of the methodology to higher connectivity levels is then proposed.