Design of an on-chip 0.13μm CMOS 6.5-7.0GHz High Gain Receiver Front-end for Wireless Communications

摘要

This paper addresses the problem of 6.5-7.0 GHz wireless communication applications within IEEE ultra-wideband (UWB) standard in a proposed directconversion receiver front-end. The front-end comprises a narrowband low-noise amplifier (LNA) and a quadrature mixer. The LNA employs two-section LC ladder topology and transconductance boosted to achieve input matching, linearization and noise improvement Characterized by folded Gilbert form, the mixer introduces PMOS devices as LO switches and onchip high-Q inductors for biasing, and thus simultaneously achieves high switch speed and sufficient conversion gain. Inductive source degeneration is also included to alleviate nonlinearity. The entire front-end captures in-band 35.1dB to 37.1dB high flat gain, 1.123dB to 1.294dB low DSB noise and 2.64 to 2.73dBm ⅡP3 by merely consuming 9.6mW from standard 1.2V supply.