3D PLUS HI-REL DDR2 TERMINATION REGULATOR MODULE A BUILDING BLOCK FUNCTION FOR HIGH RELIABILITY SDRAM DDR2 SYSTEM ARCHITECTURE

摘要

Memory system architectures using DDR2 technology need to be compliant with JEDEC JESD8-15A standard [1]. Therefore a bus termination regulator able to sink and source current while regulating VTT voltage is used for this purpose. Such module has been developed by 3D PLUS and is the first space qualified DDR Termination Regulator (DDR2-TR) available on the market. It is based on an innovative Bang-Bang regulation principle, chosen for its speed performance and to guarantee an output voltage that remains within the predefined limits regardless of any output current transients. The output filter type is selected to make the module rugged to any overload condition without complex protection circuits. The module has been specifically designed for low input voltage, low noise and high reliability systems where space is a key consideration. The module uses the 3D PLUS SIP (System-In-Package) technology embedding 3 stacked PCBs. No external filters or decoupling capacitors are needed.