Simultaneous OPC- and CMP-aware Routing Based on Accurate Closed-Form Modeling

摘要

As the process technology advances to the nanometer nodes, Optical Proximity Correction (OPC) is the most popular Resolution Enhancement Technique (RET) in industry for subwavelength lithography, and the inter-level dielectric (ILD) thickness variation caused by the planarization step of a Chemical Mechanical Polishing (CMP) process also plays a key role for interconnect yield. Considering the OPC and CMP effects simultaneously during routing can significantly alleviate the width and thickness variations (and thus the whole 3D geometry variations) of post-layout RET and CMP operations. In this paper, we first present an efficient, yet sufficiently accurate closed-form formula for printed width computation and dummy-insertion-aware routing cost derivation. The formula provides an effective cost modeling to guide a router for better post-layout OPC correction and CMP planarization. Compared with the state-of-the-art OPC-friendly router, QL-MGR (which does not consider CMP), the experimental results show that our router can achieve respective 19% and 6% reductions in the maximum and average layout distortions. Compared with the state-of-the-art CMP-aware router, TTR (which does not consider OPC), the experimental results show that our router can achieve respective 19% and 25% reductions in the peak-to-peak thickness and thickness variance. These results demonstrate that our simultaneous OPC- and CMP-aware router can lead to significant improvements for layout integrity.