For the first time, we demonstrate low-VT (VTlin ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-VT pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500µA/µm ION and 245µA/µm IEFF at 2nA/µm IOFF and VDD=0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different VT from 0.32V to 0.6V for both nMOS and pMOS, demonstrating a real multiple-VT capability for FDSOI CMOS while keeping the channel undoped and the VT variability around AVT=1.3mV.µm.
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机译:我们首次演示低V T INF>(V TLIN INF>±0.32V)通过TIN的工作功能工程,在栅极第一FDSOI技术中调整在闸门第一FDSOI技术中调整的PMOS和PMOS。 Taaln金属门。特别是,对于低V T INF> PMOS,已经研究了各种具有优化Al浓度的蒸汽沉积的Taaln叠层,以在保持良好的可靠性和移动性的同时将各种化学 - 蒸汽沉积的Taaln叠层精细地调整上层的工作功能。 500μA/μm的短沟道性能 inf>和245μA/μmi eff inf>在2na /μmi 关闭 im>和v dd inf> = 0.9V在带Taaln门的PMO上报告。另外,发现这两个金属栅极的组合在超薄埋藏氧化物(盒子)下方的N-或P掺杂接地平面(盒子)可以提供4种不同的V T IM>为0.32V对于NMOS和PMOS来说至0.6V,用于对FDSOI CMOS的实际多V T INF>能力,同时保持通道未掺杂,V T IM>可变性周围 VT inf> =1.3mv.μm。
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