A TESTBENCH FOR VALIDATION OF DST FAULT-TOLERANT ARCHITECTURES ON POWERPC G4 COTS MICROPROCESSORS

摘要

The purpose of fault tolerance studies, named TAFT,conducted at CNES is to prepare the space community forthe significant evolution linked to the usage of COTSelectronics integrated components for developingspacecraft supercomputers. CNES has patented the DMTand DT2 fault-tolerant architectures with 'light' features.The difficulties linked with COTS components use, a rationalefor COTS-based computers in space applications,then the development of a DST (i.e. DMT/DT2) testbenchbased on a PowerPC~? G4 microprocessors from e2v, arepresented in this paper.