Multiplier is one of the most important components in the modern processor, but it is extensively implemented by Modified Booth Encoding (MBE) algorithm and compressed tree architecture, both of which were proposed many years ago. A novel pipelined multiplier using Divide and Conquers (D&C) algorithm is proposed in this work. Firstly a deductive process in binary is offered to prove the D&C algorithm by means of the reduction of general multiplication's complexity. Then an example of typical 32-bit multiplication is taken to illustrate the division procedure from 32-bit to 8-bit, which is aimed to reduce the elementary multiplications in light of D&C algorithm. Finally a 32-bit pipelined multiplier using D&C algorithm is constructed and implemented in Xilinx FPGA. Post simulation after synthesis certifies the performance of the designed multiplier is higher than that of array or parallel one with MBE algorithm.
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