A New Bit Synchronization Clock Extraction Scheme and FPGA Implementation

摘要

In order to achieve reliable synchronization in digital receiver, we proposed a new scheme to extract the bit synchronization clock, by capturing and realtime tracking of the matched filter output Zerocrossing position. By comparing two adjacent sample values of the matched filter output signal to capture the Zero-crossing position, and then record the follow-up Zero-crossing relative offset to the initial Zero-crossing position, adjust the Zerocrossing position in real time to track synchronization process, and extract a higher bit precision synchronous clock. This bit synchronization program is simple and reliable, with high precision, little affected by noise, and consume less FPGA resources, easy to implement.