The FPGA Dynamic Partial Reconfiguration Implementation of Crossbar Scheduling Algorithm

摘要

FPGA dynamic partial reconfiguration (DPR) tends to be adopted for its flexibility and fewer resource consumption increasingly in hardware implementation, especially in communication devices. However, the effective of DPR device is often limited by the overhead of the reconfiguration. A crossbar scheduling algorithm is used to schedule the crossbar, or decide the order in which cells will be served. The iSlip and FIRM are classic crossbar scheduling algorithms, but they do not support DPR. The paper is concerned with accelerating the reconfigurable platform to reduce reconfigurable overhead of crossbar scheduling algorithm. With the development of DPR, implementation of these algorithms will have improvement both in performance and resource usage. In this paper, we compared the DPR implementation and non-DPR implementation and found that the former achieves average 1.168 speedup under 20000 sets 16 bits data which simulate the i.i.d. Bernoulli arrivals in 4x4 crossbar. And DPR also reduces 41.897% Slices in 4x4 crossbar.