DoE applied to two-level memory hierarchies for energy consumption reduction

摘要

Tuning cache architectures in platforms for embedded applications can dramatically reduce energy consumption. This paper presents an optimization mechanism based on the Design of Experiments (DoE) for adjusting two-level cache memory hierarchies in order to reduce the energy consumption of embedded applications. DoE is a technique used to plan experiments and in this work it was adapted for the architecture exploration problem. Preliminary results for 6 applications from the Mibench benchmark suite show an average reduction of about 6% in the energy consumption for data caches, and it has shown itself to be simpler and with lower computational cost, when compared to existing heuristics.