In this paper, we propose the first chemical-mechanical polishing (CMP) aware application-specific three-dimensional (3D) network-on-chip (NoC) design that minimizes through-silicon-via (TSV) height variation, thus reduces its bonding failure, and meanwhile optimizes conventional NoC design objectives. Our 3D NoC design assigns cores to proper silicon layers, determines the 3D NoC topology, allocates routing paths, and then floorplans cores, routers and TSV arrays by a CMP-aware manner. The key idea behind this 3D NoC design flow is to determine the CMP-aware 3D NoC topology where TSV arrays with low and uniform metal density are inserted between adjacent layers. Experimental results show that our CMP-aware 3D NoC design can achieves lower TSV height variation, higher performance and lower power consumption than the previous state-of-the-art 3D NoC designs.
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机译：在本文中，我们提出了第一个具有化学机械抛光（CMP）功能的，专用于应用的三维（3D）片上网络（NoC）设计，该设计可最大程度地减小硅通孔（TSV）的高度变化，从而降低其通孔焊接失败，同时优化常规的NoC设计目标。我们的3D NoC设计将内核分配给适当的硅层，确定3D NoC拓扑，分配路由路径，然后以可感知CMP的方式对内核，路由器和TSV阵列进行平面布置。此3D NoC设计流程背后的关键思想是确定可识别CMP的3D NoC拓扑，其中将金属密度低且均匀的TSV阵列插入相邻的层之间。实验结果表明，与之前的最新3D NoC设计相比，我们具有CMP意识的CMP 3D NoC设计可以实现更低的TSV高度变化，更高的性能和更低的功耗。
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