Power and energy issues have significantly gained in importance in computing environments in the last few decades. In a world of mobile devices and massive-scale data centers, low-power systems are crucial for cost, availability, and the environment. Minimizing power consumption in a computing system is a complex problem that can be addressed with various strategies and on various levels. In this paper we focus on System-on-Chip (SoC), and in particular on power-efficient Network-on-Chip (NoC) topologies. The popular saying that “there ain''t no such thing as a free lunch” applies to computing systems likewise. In the quest for power and performance optima in the design space of NoC, we investigate non-local interconnect architectures for SoC. By adopting a complex network perspective and by employing an optimization technique, we show that small-world networks with power-law distance-dependent wire-length distributions are more power-efficient while offering the same performance than simple small-world topologies. We argue that such networks occupy optimal spots in the design space of NoCs. Our results are particularly relevant for addressing the scalability problem of global (or long-range) links, for building more power-efficient computers, and for emerging computing devices built through self-assembly.
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