A quiescent power-aware low-voltage output capacitorless low dropout regulator for SoC applications

摘要

This paper presents a new low-voltage output capacitorless low dropout (LDO) voltage regulator for System-on-Chip (SoC) applications. A low-impedance loading network is introduced at the output of LDO to achieve full range stability from 0 to 100 mA load current at a 100 pF parasitic capacitance load. No minimum output load current is needed whereas the quiescent current is made low. Thus, it improves the efficiency for light load currents. The proposed LDO has been validated using BSIM3 models and GLOBALFOUNDRIES 0.18-µm CMOS process. The simulation results have shown that the LDO consumes only 14 µA at 0 load current, regulating the output at 1 V from a minimum 1.2 V supply, with a dropout of 200 mV at the maximum load current of 100 mA. The worst case full-load transient response is about 3.96 µs.