Detecting race conditions in asynchronous DMA operations with full system simulation

摘要

In this paper, we describe a technique for detecting race conditions between direct memory access (DMA) operations and load/store instructions using a full system simulator. Our approach uses event monitoring features of a full system simulator to monitor DMA operations and the memory areas they access and detect conflicting accesses that could represent races conditions. Our race condition checker tracks DMA operations from the time they are issued until they are architecturally guaranteed to be complete, rather than simply tracking when they actually complete, and thus detects race conditions in programs even when the actual data accesses do not occur out of order. This feature is valuable because the mechanisms for ensuring ordering of asynchronous DMA operations are complex and often poorly understood by application programmers. These DMA operations may conflict with each other or with loads and stores performed by processor that initiated the operations, creating ample opportunity for race conditions to occur. We describe our race condition checker in detail and show how it can be used to easily detect race conditions in DMA operations initiated by special purpose cores.