A 1.2 V Low-power Receiver for Short Range Applications

摘要

In this paper, a 1.2-V 2.4 GHz low power receiver front-end for wireless sensor node is demonstrated in standard 0.18 |im CMOS technology, which consists of an LNA, an active balun, and a sub-harmonic passive mixer. The measurement results of the proposed circuit show a low power consumption of 8.7 mw, 8dB noise figure, 18 dB conversion gain and a third-order intercept point (IIP3) of-15dBm. In this design, a common-source (CS) staged LNA is adopted to achieve high gain as well as low noise figure. A balun is connected successively to provide a single-to-differential transformation which enhances the immunity to the noise from the power supply. A sub-harmonic mixer is used to minimize the dc-offset issue, which also results in a less required LO power and the DC power consumed by the LO buffers in the mean time. The active part of this circuit only occupies 0.71mm x 0.37 mm of chip area. The measurement results exhibit that this sub-harmonic receiver front-end is promising for short range wireless sensor network application.