Modular exponentiation is an important operation in several public-key cryptosystems. It is performed using successive modular multiplications. For the sake of efficiency, one needs to reduce the total number of required modular multiplications. In this paper, we propose an efficient hardware implementation for computing modular exponentiations using the the concept of addition chain. This implementation use an addition chain tailored for the exponent to compute the modular power and evolved by a genetic algorithm. The system-on-chip (SoC) methodology is used to yield a hardware/software co-design of the modular exponentiation that takes advantage of the evolved addition chain. We provide a comparison of the proposed implementation to three existing ones using the performance factor, which takes into account both space and time requirements.
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