Testable combinational circuit design based on ZDD-implementation of ISOP Boolean function

摘要

It is found out that a set of test patterns for all multiple stuck-at faults at the CLBs poles of combinational circuit in the frame of FPGA technology coincides with the set of test for all single stuck-at faults of irredundant sum-of-products describing the combinational circuit behavior. The combinational circuit designed based on ZDD-implementation of irredundant sum-of-products.