Mapping SMV models to event-B models

摘要

This paper presents an approach which integrates two formal verification techniques, model checking and the Event-B method in a way that makes it possible to benefit from the advantages of both methods in the design flow. This integration allows the user to write his model and verifies it using model checking techniques/tools. If the model has errors or unverified properties the model checking produced counterexamples and simulation facility can be used to correct the model, this procedure can be repeated till a correct model is produced and verified. The verified model is then automatically translated to the corresponding Event-B model. The translated model can then be further analyzed by the Event-B tool and the user can utilize all the Event-B available tools. The generated model can also be further refined towards a more detailed model that can be used to generate the corresponding C code for the original system.