Since their apparition, Field-Programmable Gate Arrays (FPGAs) have become the most popular implementation media for digital circuits. But like the most of the other devices, the FPGA has some disadvantages to be optimized. Those limits are essentially: the low speed, the limited resources and area overhead. The main goal of this paper is to improve the area efficiency constraint. To achieve this; we proposed a technique to improve the placement of an application Netlist on a particular architecture of an FPGA. This technique consists in spreading out the congested zones in order to reduce the channel width required in the routing phase. If the CLBs placement is optimized to reduce congestion, the router will use less routing resources and the area will be reduced. Thus, we can call it a routability-driven placement.
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