The minimum operating voltage, Vmin, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using a timing margin is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the threshold-voltage variations, ΔVt, which become more significant with device scaling, and to the lowest necessary threshold voltage, Vt0, of MOSFETs. As a result of comparing the Vmins of logic, SRAM, and DRAM blocks, it turns out that the SRAM block is problematic because it has the highest Vmin despite using RAM repair techniques. Various techniques are thus reviewed, including shortening the data line, up-sizing the MOSFETs, and control of the common source line or the word line. To further reduce the Vmins of the blocks, ΔVt-immune MOSFETs such as a planar fully-depleted structure (FD-SOI) and fin-type structure (FinFET), and low-Vt0 circuits are discussed, showing the below 0.5-V CMOS era to be feasible to come.
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机译：研究了存储器丰富的纳米级CMOS LSI的最小工作电压V min ，以打开低于0.5V时代的大门。提出了一种使用时序余量的新方法来评估V min 。结果表明，V min 对阈值电压变化ΔV t 非常敏感，该变化随器件规模的变化而变得越来越大，并且对最低的必要阈值电压V < MOSFET的inf> t0 。比较逻辑，SRAM和DRAM块的V min 的结果，发现SRAM块是有问题的，因为尽管使用了它，但它具有最高的V min RAM修复技术。因此审查了各种技术，包括缩短数据线，增大MOSFET的尺寸以及控制公共源极线或字线。为了进一步降低模块的V min s，采用ΔV t 免疫MOSFET，例如平面全耗尽结构（FD-SOI）和鳍型结构（FinFET） ），并讨论了低V t0 电路，表明下面的0.5-V CMOS时代是可行的。
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