Implementation of Speed Match Circuit Design between DSP and Peripheral Chips Using CPLD

摘要

In some industry instrument and automation equipment, the digital signal processor (DSP) usually needs establishing the interface with different speed peripheral chips. TMS320Cxx provide two kinds of mechanism to match with out side chips. One can insert 0~7 wait periods by setting inner control register. Another is to provide the READY signal pin, it can produce arbitrarily number of wait period with the exterior control circuit. In this paper, CPLD is employed to generate the waiting sign by the correlative hardware circuit diagram and VHDL language programs method respectively. The speed match circuits have been realized between DSP and peripheral chips. It can simplify the program and raise the whole performance speed of system.