首页> 外文会议>2010 2nd International Conference on Information Technology Convergence and Services >A Fast Test Architecture for Asynchronous Network-on-Chip Routing Networks
【24h】

A Fast Test Architecture for Asynchronous Network-on-Chip Routing Networks

机译:异步片上网络路由网络的快速测试架构

获取原文

摘要

ANoC (Asynchronous Network-on-Chip) has been developed to solve problems of large number of cores in SoC (System-on-Chip) by giving asynchronism to every core. This new architecture requires new Testing methods different from the existing SoC Test, and it freshly needs the test of router and routing networks. This paper first offers high-speed testing architecture that tests more than one routers and networks at the same time in the 2-D mesh topology. Then, the structure of wrapper for realization of this method is explained. We show that the more number of routers is, the more effective performance is by checking the clock count for test of various ANoCs that have several sizes.
机译:已经开发出ANoC(异步片上网络)以通过使每个内核具有异步性来解决SoC(片上系统)中大量内核的问题。这种新架构需要不同于现有SoC测试的新测试方法,并且刚需要路由器和路由网络的测试。本文首先提供了一种高速测试架构,该架构可以在2-D网状拓扑中同时测试多个路由器和网络。然后,说明用于实现该方法的包装器的结构。我们通过检查时钟数以测试具有多种大小的各种ANoC来表明,路由器数量越多,性能越有效。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号