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Coded IDMA system performance with parallel interleavers

机译:具有并行交织器的编码IDMA系统性能

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In this paper we evaluate the use of parallel interleavers for user separation in coded IDMA systems. The parallel interleavers have previously been evaluated for uncoded systems, and we here present extended results for the coded case. The new results are important for real systems, as they will most likely use performance enhancing channel coding. The parallel interleavers are designed to remove the risk of memory access collision during interleaving. These problems may occur when the interleaving process is being parallelized in order to support parallel processing at the decoder. The results show that the degree of parallelization in the interleaver design has an insignificant effect on the considered coded system performance. Furthermore, our results also show that the use of parallel interleavers gives a performance that is similar to that obtained when using random interleavers.
机译:在本文中,我们评估了在编码IDMA系统中使用并行交织器进行用户分离的情况。并行交织器以前已针对未编码的系统进行了评估,在此我们提供了编码情况下的扩展结果。新结果对实际系统很重要,因为它们很可能会使用性能增强的信道编码。并行交织器旨在消除交织期间内存访问冲突的风险。当交错处理被并行化以支持解码器处的并行处理时,可能会出现这些问题。结果表明,交织器设计中的并行度对所考虑的编码系统性能影响不大。此外,我们的结果还表明,使用并行交织器可提供与使用随机交织器时相似的性能。

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