In this paper, the impact of gap-fill planarity on Multi-Self-Aligned Block, SADP (self-aligned double patterning) process for advanced optical technology nodes (7 nm/5 nm) interconnects was studied through process emulations. This study specifically focuses on the insertion of an etch stop layer (ESL) between two coatings of organic planarization layer (OPL), referred to as the tri-layer PM (pattern mask), which enables a thinner OPL for pattern transfer while adding topography correction for non-mandrel block patterning processes. This scheme reduces pillar aspect ratio for improved CD control and flop-over mitigation, as well as topography correction to mitigation false metal patterns in field regions. However, ESL could cause CD variation if it was deposited on the sidewall of spacer where it is a function of the conformality of ESL deposition.
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