A high stability low drop-out regulator with fast transient response

摘要

This paper presents a high stability, fast transient response, low-dropout voltage regulator (LDO) with a novel stepping several stages Miller capacitance frequency compensation and a slew-rate enhanced (SER) circuit. The proposed frequency compensation scheme can guarantee the LDO stable for the entire load. By utilizing the SRE circuit, the proposed LDO provides fast settling time and small voltage variation for a pulsed output current of 0 to Imax. Implemented in a 0.35-µm CMOS process, the proposed LDO achieve 80 degree phase margin and a PSR of 60 dB at 10kHZ. The proposed SRE circuit improves the transient response with 110mV voltage variation and 0.5µS settling time for a 250mA load step. The maximum output current is 250mA and the regulatered output voltage is 2.5V. The proposed LDO consumes only 20µA of ground current at no load condition. The load and line regulation are 40µV/mA (ΔIload=250mA) and 2mV/V (ΔVDD=2V).