Digital asynchronous signal interpolation and clock domain crossing

摘要

This paper presents a novel concept for digital resampling and interpolation between two asynchronous clock domains. The proposed concept simplifies the resampling by eliminating the oversampling and decimation steps. Thus, conversion between sample frequencies of over 100 MHz become feasible with this concept. This interpolation filter can be used for digital-centric transmitter frontends which operate in a carrier frequency dependent clock domain. Hence, a conversion from the crystal oscillator clock domain of the digital signal processor for baseband generation is necessary. The concept is mathematical evaluated and verified with system simulations. The implementation is designed in a hardware description language, thereafter synthesised and verified with back-simulations.