Efficient implementation of intermediate frequency signal processor based on FPGA

摘要

This paper presents an available radio frequency signal processing unit software structure model. The model includes the direct frequency synthesis (DDS), down-sampling filter (CIC) and low pass filter (FIR). To reduce the hardware consumption and achieve high design efficiency, CAD tools were used and combined with specific and comprehensive VERILOG description. It can be seen from the results that IF signal processing unit in the xc4vsx25 in 200 MHz clock frequency is high-speed operated.