A dB-linear programmable gain amplifier (PGA)utilizing weighted input transistors, is implemented in a 0.18 μm CMOS process. The weighed input transistor units with constant current-density enable insensitive gain-steps while maintaining the load impedance condition. The gain range can cover from -18 dB to +30 dB in 6 dB steps, and the gain error is less than 1 dB. The 3 dB bandwidth (BW) is 60 MHz and the P1dB is -36 dBm at the maximum gain. The chip area is as small as 0.12 mm2 and the total power consumption is only 2.5 mW under 1.8 V supply.
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