In this paper, we present new systematic method for the design of an analog PID controller, applied to the voltage-mode step-down (buck) DC/DC converters. The method relies on the specification of trajectory of the load transient response. Particularly, we are interested to design a controller limiting the voltage under/overshoot to its lowest possible value. It is shown that this lowest possible value is related to the serial resistance of the output LC filter capacitor. We present a mathematical analysis of the method which is based on average model of the converter. Obtained relationships allow simple using of the method with operational amplifier based controllers. The design is validated by measurements on circuits with integrated 0.25 μm CMOS power stage.
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