Hardware oriented algorithm analysis and modification for high definition AVS video encoder VLSI implementation Digest of technical papers

摘要

In AVS video coding standard, some algorithms consume huge computation with relatively little coding performance contribution, and some algorithms create data dependencies that are harmful for efficient hardware pipeline. This paper focuses on hardware oriented algorithm analysis and modification. Motion estimation and mode decision algorithms are reviewed and modified to a hardware friendly configuration for high definition (HD) AVS video encoder VLSI implementation. The resulting performance penalties are simulated and analyzed.