Advanced Encryption Standard (AES) is the current encryption standard adopted by U.S. government and plays an important role in cryptograph systems. In this paper, AES was transferred into a stream and variant compact architectures are studied. On-the-fly key scheduling schema is also used. Pure logic based and distributed RAM based SBoxes are both implemented for the purpose of best speed and area. Pipelined architecture is also studied to achieve a better throughput. Different memory schemas are navigated, including 2-bank distributed RAM, 2-bank block RAM, shiftregister in LUT, 1-bank registers and dual-port memory. 8-bit, 32-bit, 64-bit Datapath versions are implemented to get the best throughput/area ratio. The whole design is targeted to Xilinx Spartan 3 FPGAs. The 32-bit architecture had a maximum clock frequency of 50.0 MHz and used 341 slices on the Spartan-3, a throughput of 118.5 Mbps. The pipelined 32-bit architecture had a maximum clock frequency of 125.1 MHz and used 422 slices on the Spartan-3, a throughput of 296.49 Mbps. The results show that our implementation has a good potential to fit to stream cipher requirements.
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