Architectural enhancements in Stratix-III™ and Stratix-IV™

摘要

This paper describes architectural enhancements in the Stratix-III" and Stratix-IV" FPGA architectures. These architectures feature programmable power management, which allows the power and performance of logic and routing to be varied to minimize total power without any performance loss. This paper describes the technique used for programmable power management, and describes the experimental evaluation that led to the choice of regions in these architectures. The memory architecture is also explored by adding heterogeneous memory mapping to the FPGA Modeling Toolkit, and used to explore LUT based memory structures. The ALM structure provides more inputs than required for a simple 6 LUT, which can be used with simple modifications to efficiently support simple dual-ported LUT based RAM. Replacing the Stratix-II" small memory blocks with LUT RAM and changing the size of other two memories is shown to reduce overall core area across a set of benchmark designs.