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The Cache-Core Architecture to Enhance the Memory Performance on Multi-Core Processors

机译:高速缓存核心体系结构可增强多核处理器上的内存性能

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Multi-core architectures are focused on improving the processor performance. However, multi-core processors cannot achieve their peak performance when application program has a little thread level parallelism. On the other hand, it is difficult to extract thread level parallelism from application programs. Because of these factors, in this paper, we propose the cache-core. The cache-core is a mechanism where the excess core behaves like an L2 data cache by executing software managed cache program. As the cache-core supplies other core with data as an L2 cache, the number of global memory accesses can decrease. So the cache-core enhances the performance of multi-core processor. We evaluate the cache-core on Cell/B. E. processor in detail. Our evaluation results show that the cache-core can improve computational performance. Furthermore, this paper describes consideration of the cache-core for a many-core processor. We evaluate the cache-core when a lot of cores massively access the global memory. The evaluation results show effectiveness of the cache-core on a many-core processor.
机译:多核体系结构专注于提高处理器性能。但是,当应用程序的线程级并行度很小时,多核处理器将无法达到其最佳性能。另一方面,很难从应用程序中提取线程级并行性。由于这些因素,在本文中,我们提出了缓存核心。高速缓存核心是一种机制,其中多余的核心通过执行软件管理的高速缓存程序来像二级数据高速缓存一样工作。由于缓存核心为其他核心提供数据作为二级缓存,因此可以减少全局内存访问的数量。因此,高速缓存核心可增强多核处理器的性能。我们评估Cell / B上的缓存核心。 E.处理器的详细信息。我们的评估结果表明,缓存核心可以提高计算性能。此外,本文描述了多核处理器对高速缓存核的考虑。当许多核心大规模访问全局内存时,我们评估缓存核心。评估结果显示了高速缓存核在多核处理器上的有效性。

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