This paper presents a novel substrate coupling simulationtool that is well suited to floorplanning of large mixed-signalIC designs. The IC layout may consist of severalsubcircuits, hence a hierarchical design flow, which is usuallyused for IC circuit design and layout, is supported.Coupling data modelling the substrate inside subcircuitsare precalculated and subsequently used during floorplanningleading to shorter simulation time. In addition, theimpedance model of the power grid is considered as wellmaking it possible to provide estimation results of substratecoupling quickly after only one simulation step. The approachis verified by experimental results in 0.13m CMOSand 0.25m BiCMOS technologies.
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