An improved macro-model for simulation of single electron transistor (SET) using HSPICE

摘要

To get a more accurate model for simulation of single electron transistors (SETs), we have proposed a new macro-model that includes the ability of electron tunneling time calculation. In our proposed model, we have modified the previous models and applied some basic corrections to their formulas. In addition, we have added a switched capacitor circuit, as a quantizer, to calculate the electron tunneling time. We used HSPICE for high-speed simulation and observed that the simulation results obtained from our model matched more closely with that of SIMON 2.0. We also could evaluate the time of electron tunneling through the barrier by using the quantizer. Clearly, our macro-model gives more accurate results than of the other models when compare with SIMON 2.0, and can be used for calculating the delay time of complicated circuits.