Recently, FPGAs have been integrated into HPC clusters in order to boost computational performance while reducing power consumption. However, performance and effective logic utilisation is usually limited by the number of inter-device pins and most importantly the interconnection architecture. Mesh interconnection in particular suffers from the pin-limitation problem. The concept of Virtual Wires has been proposed to reduce the impact of this problem by using time-multiplexed physical wires. This paper demonstrates a simple yet effective technique to further reduce the number of the physical wires required by the Virtual Wires and the Mesh architectures by an average of 18% over the original routing algorithms. This technique can be equally applied to exploit the topological properties of any mesh-based architecture.
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