Double dipole RET investigation for 32 nm metal layers

摘要

For 32 nm test chips, aggressive resolution enhancement technology (RET) was required for lx metal layers to enable printing minimum pitches before availability of the final 32 nm exposure tool. Using a currently installed immersion scanner with 1.2 numerical aperture (NA) for early 32 nm test chips, one of the RET strategies capable of resolving the minimum pitch with acceptable process latitude was dipole illumination. To avoid restricting the use of minimum pitch to a single orientation, we developed a double-expose/single-develop process using horizontal and vertical dipole illumination. To enable this RET, we developed algorithms to decompose general layouts, including random logic, interconnect test patterns, and SRAM designs, into two mask layers: a first exposure (E1) of predominantly vertical features, to be patterned with horizontal dipole illumination; and, a second exposure (E2) of predominantly horizontal features, to be patterned with vertical dipole illumination. We wrote this algorithm into our OPC program, which then applies sub-resolution assist features (SRAFs) separately to the El and E2 masks, coordinating the two to avoid problems with overlapping exposures. This was followed by two-mask OPC, using El and E2 as mask layers and the original layout (single layer) as the target layer. In this paper, we describe some of the issues with decomposing layout by orientation, issues that arise in SRAF application and OPC, and some approaches we examined to address these issues.